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The maximum test temperature should be below the Tg of the printed circuit board, for FR-4 below about 110 C. At Tg, the CTE of the board increases rapidly, but many other properties also change; for example, the elastic modulus of the board decreases. To avoid approaching the melting temperature of the solder and changing the mechanism of solder creep, the maximum temperature should also be kept below about 0.9Tm, where Tm is the melting temperature of the solder in Kelvin. For eutectic Sn-Pb solder, Tm is 137 C, well above Tg. But for printed circuit board materials with high Tg values or low-meltingtemperature solders, this restriction may take precedence. Using a peak temperature above these limits results in unpredictable acceleration. The minimum temperature should be high enough that creep is still the primary deformation mechanism of the solder, that is, at least 0.5 Tm, or 45 C for eutectic Sn-Pb solder. Many investigators prefer a higher minimum temperature ( 20 or 0 C) to ensure that creep occurs fast enough to relieve the imposed shear stress during the allowed dwell time. Using too low a minimum temperature may seem to increase the acceleration factor (increased T ) while actually decreasing it (decreased ), resulting in an overly optimistic life prediction.

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Don t look back. If a questioner begins to dominate the Q&A period, do not look back at her as you conclude your answer. Turn your eyes to another part of the room as you nish speaking. This is a polite, nonverbal way to stop the questioner from dominating your time.

25 C

The rate of temperature cycling should not exceed 20 C/min and the dwell time at the temperature extremes should be at least 5 min. The purpose of controlling the cycling speed is to minimize thermal shock and the stresses associated with differential heating or cooling. The dwell time at the temperature extremes is an absolute minimum needed to permit creep to occur. A longer dwell time is recommended, particularly at the minimum temperature.

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As described here, there are several acceleration factors in the literature that may be applied to make life estimations from the accelerated test data that may be obtained using a thermal profile that fits the preceding criteria. One of the simplest expressions is due to Norris and Landzberg: nop Nop = n test Ntest where

Nop and Ntest = life under operating and accelerated test conditions, respectively n = cycling frequency f = mean temperature47

Another widely used expression may be found in IPC-SM-785. This expression tries to account for the effect of power cycling and the dwell time in the thermal profile; it also makes it possible to make predictions for one component or solder joint geometry based on data for another similar one. In its most simplified form, the acceleration factor for tests meeting the preceding criteria for FR-4 and eutectic Sn-Pb solder joints may be approximated as Nop Top2.4 = Ntest Ttest Top4 Nop = Ntest Ttest for leadless surface-mount attachments for compliant-leaded surface-mount attachments

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assuming the test assemblies are nearly identical to the assemblies that will be put into service. Mechanical fatigue cycling is increasingly being used as a quick way to induce solder joint failures. The goal is to simulate the thermal fatigue failure process in a much shorter test. The validity of this approach is still being investigated; although the imposed strain in each cycle is intended to be the same, the mechanical test eliminates thermomechanical effects (including creep) because the cycles are about two orders of magnitude faster. Nonetheless, mechanical cycling can certainly provide useful comparisons between different designs or package

styles. The tests are usually conducted at a constant temperature with fixturing that puts the solder joints in shear when bending or tensile displacements are applied. 57.6.3.2 Mechanical. Mechanical vibration and shock can cause solder joint failures, particularly for large, rigid components or components with large, heavy heat sinks. Mechanical shock tests are usually modeled after drops that may occur during transportation or use. The test drops are generally quite severe, but few in number, since the system is not expected to be subjected to repeated drops in service. One common test uses a maximum acceleration of about 600 g, a maximum velocity of about 300 in/s, and a shock pulse of about 2.5 ms duration. The test setup is shown schematically in Fig. 57.26.

FIGURE 57.26 Schematic of setup used to test the resistance of printed circuit assemblies to out-of-plane mechanical vibration and shock.

On the other hand, the PCA may be exposed to millions of mechanical vibration cycles during its lifetime.48 Depending on the application, both in-plane and out-of-plane vibration may play an important role. The damage done by these cycles depends primarily on whether the cycling frequency is near a natural frequency of the board, where large deflections can take place. For in-plane vibration, random vibration over a wide excitation frequency range is performed at a constant power spectral density. Most surface-mount components have high natural frequencies, and solder joint failures are rarely observed. For out-of-plane vibration, the following procedure is recommended:

Design and fixture the test board so that each specimen is clamped at both ends and contains a single component at the center (see Fig. 57.26). Impose the vibration using a shaker table with sinusoidal excitation. Find the natural frequency of the sample by sweeping the frequency at a low amplitude (to prevent inadvertent damage before the start of the test). This natural frequency is near, but not the same as, the natural frequency at the larger amplitude that will be used for testing. Conduct the test by sweeping the frequency in a narrow range around the natural frequency previously determined. The amplitude can be set to correspond to a certain power spectral density or to achieve a desired deflection of the PCB.

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